OUT2=Val_0x0, LOOPBACK=Val_0x0, OUT1=Val_0x0, DTR=Val_0x0, RTS=Val_0x0, AFCE=Val_0x0
Modem Control Register
| DTR | Data Terminal Ready This bit is used to directly control the DTR output. The value written to this bit is inverted and driven out on DTR. The DTR output is used to inform the modem that the UART is ready to establish communications. Note that in Loopback mode (UART_MCR[LOOPBACK] set to 1), the DTR output is held inactive high while the value of this bit is internally looped back to an input. 0 (Val_0x0): DTR output deasserted (logic1) 1 (Val_0x1): DTR asserted (logic 0) |
| RTS | Request to Send This bit is used to directly control the UART_RTS signal. The RTS bit is used to inform the modem that the UART is ready to exchange data. When Auto Flow Control mode is not enabled (UART_MCR[AFCE] set to 0), the UART_RTS is set low by programming UART_MCR[RTS] to high. In Auto Flow Control and FIFOs enable (UART_FCR[FIFOE] set to 1), the UART_RTS is controlled in the same way, but is also gated with the Rx FIFO threshold trigger (UART_RTS is inactive high when above the threshold). The UART_RTS signal will be deasserted when UART_MCR[RTS] set to 0. Note that in Loopback mode (UART_MCR[LOOPBACK] set to 1), the UART_RTS output is held inactive high while the value of this bit is internally looped back to an input. 0 (Val_0x0): UART_RTS deasserted (logic 1) 1 (Val_0x1): UART_RTS asserted (logic 0) |
| OUT1 | This bit is used to directly control the OUT1 output. The value written to this location is inverted and driven out on OUT1. Note that in Loopback mode (UART_MCR[LOOPBACK] set to 1), the OUT1 output is held inactive high while the value of this location is internally looped back to an input. 0 (Val_0x0): OUT1 output deasserted (logic 1) 1 (Val_0x1): OUT1 output asserted (logic 0) |
| OUT2 | This bit is used to directly control the OUT2 output. The value written to this location is inverted and driven out on OUT2. Note that in Loopback mode (UART_MCR[LOOPBACK] set to 1), the OUT2 output is held inactive high while the value of this location is internally looped back to an input. 0 (Val_0x0): OUT2 output deasserted (logic 1) 1 (Val_0x1): OUT2 output asserted (logic 0) |
| LOOPBACK | Loopback Bit This bit is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode, data on the UART_TX is held high, while UART_TX is looped back to the UART_RX, internally. In this mode all the interrupts are fully functional. In Loopback mode, the modem control inputs are disconnected and the modem control outputs are looped back to the inputs internally. 0 (Val_0x0): Loopback mode disabled 1 (Val_0x1): Loopback mode enabled |
| AFCE | Auto Flow Control Enable When this bit is set and FIFOs are enabled, Auto Flow Control features are enabled. 0 (Val_0x0): Auto Flow Control mode disabled 1 (Val_0x1): Auto Flow Control mode enabled |